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high speed, half-duplex i coupler ? isolated rs-485 transceiver adm2486 rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the prop erty of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2005 analog devices, inc. all rights reserved. features half-duplex, isolated rs-485 transceiver profibus?-compliant ansi eia/tia 485-a and is o 8482: 1987(e) compliant 20 mbps data rate 5 v or 3 v operation (v dd1 ) high common-mode transient immunity: >25 kv/s isolated de status output receiver open-circuit, fail-safe design thermal shutdown protection 50 nodes on bus safety and regulatory approvals ul recognition2500 v rms for 1 minute per ul 1577 csa component acceptance notice #5a vde certificate of conformity din en 60747-5-2 (vde 0884 part 2): 2003-01 din en 60950 (vde 0805): 2001-12; en 60950: 2000 v iorm = 560 v peak operating temperature range: ?40c to +85c wide body, 16-lead soic package applications isolated rs-485/rs-422 interfaces profibus networks industrial field networks multipoint data transmission systems general description the adm2486 differential bus transceiver is an integrated, galvanically isolated component designed for bidirectional data communication on multipoint bus transmission lines. it is designed for balanced transmission lines and complies with ansi eia/tia-485-a and iso 8482: 1987(e). functional block diagram rts v dd1 de gnd 1 a b v dd2 gnd 2 galvanic isolation logic side txd rxd bus side 04604-001 re pv adm2486 figure 1. the device employs analog devices i coupler technology to combine a 3-channel isolator, a three-state differential line driver, and a differential input receiver into a single package. the logic side of the device is powered with either a 5 v or a 3 v supply, and the bus side uses an isolated 5 v supply. the adm2486 driver has an active-high enable feature. the driver differential outputs and the receiver differential inputs are connected internally to form a differential input/output port that imposes minimal loading on the bus when the driver is disabled or when v dd1 or v dd2 = 0 v. also provided is an active- high receiver disable feature that causes the receive output to enter a high impedance state. the device has current-limiting and thermal shutdown features to protect against output short circuits and situations where bus contention might cause excessive power dissipation. the part is fully specified over the industrial temperature range and is available in a 16-lead, wide body soic package.
adm2486 rev. c | page 2 of 20 table of contents specifications..................................................................................... 3 timing specifications....................................................................... 5 absolute maximum ratings............................................................ 6 esd caution.................................................................................. 6 adm2486 characteristics ............................................................... 7 package characteristics ............................................................... 7 regulatory information............................................................... 7 insulation and safety-related specifications............................ 7 vde 0884 insulation characteristics ........................................ 8 pin configuration and function descriptions............................. 9 test circuits..................................................................................... 10 switching characteristics .............................................................. 11 typical performance characteristics ........................................... 12 circuit description......................................................................... 14 electrical isolation...................................................................... 14 truth tables................................................................................. 14 power-up/power-down thresholds ....................................... 14 thermal shutdown .................................................................... 15 receiver fail-safe inputs ........................................................... 15 magnetic field immunity.......................................................... 15 applications information .............................................................. 16 power_valid input ..................................................................... 16 isolated power supply circuit .................................................. 17 outline dimensions ....................................................................... 18 ordering guide .......................................................................... 18 revision history 3/05rev. b to rev. c change to package characteristics................................................. 7 changes to figure 12, figure 14, and figure 15 ......................... 11 change to power_valid input section......................................... 16 1/05rev. a to rev. b added profibus logo ................................................................... 1 11/04rev. 0 to rev. a changes to figure 1.......................................................................... 1 changes to figure 6........................................................................ 10 added figure 22 through figure 25............................................. 13 updated outline dimensions ....................................................... 18 changes to ordering guide .......................................................... 18
adm2486 rev. c | page 3 of 20 specifications 2.7 v v dd1 5.5 v, 4.75 v v dd2 5.25 v, t a = t min to t max , unless otherwise noted. table 1. parameter min typ max unit test conditions/comments driver differential outputs differential output voltage, v od 5 v r = , see figure 3 2.1 5 v r = 50 ? (rs-422), see figure 3 2.1 5 v r = 27 ? (rs-485), see figure 3 2.1 5 v v tst = ?7 v to 12 v, v dd1 4.7, see figure 4 ? |v od | for complementary output states 0.2 v r = 27 ? or 50 ?, see figure 3 common-mode output voltage, v oc 3 v r = 27 ? or 50 ?, see figure 3 ? |v oc | for complementary output states 0.2 v r = 27 ? or 50 ?, see figure 3 output short-circuit current, v out = high 60 200 ma ?7 v v out +12 v output short-circuit current, v out = low 60 200 ma ?7 v v out +12 v bus enable output output high voltage v dd2 ? 0.1 v i ode = 20 a v dd2 ? 0.3 v dd2 ? 0.1 v i ode = 1.6 ma v dd2 ? 0.4 v dd2 ? 0.2 v i ode = 4 ma output low voltage 0.1 v i ode = ?20 a 0.1 0.3 v i ode = ?1.6 ma 0.2 0.4 v i ode = ?4 ma logic inputs input high voltage 0.7 v dd1 v txd, rts, re , pv input low voltage 0.25 v dd1 v txd, rts, re , pv cmos logic input current (txd, rts, re , pv) ?10 0.01 10 a txd, rts, re , pv = v dd1 or 0 v receiver differential inputs differential input threshold voltage, v th ?200 200 mv ?7 v v cm +12v input hysteresis 70 mv ?7 v v cm +12v input resistance (a, b) 20 30 k? ?7 v v cm +12v input current (a, b) 0.6 ma v in = +12 v ?0.35 ma v in = ?7 v rxd logic output output high voltage v dd1 ? 0.1 v i out = 20 a, v a ? v b = 0.2 v v dd1 ? 0.4 v dd1 ? 0.2 v i out = 4 ma, v a ? v b = 0.2 v output low voltage 0.1 v i out = ?20 a, v a ? v b = ?0.2 v 0.2 0.4 v i out = ?4 ma, v a ? v b = ?0.2 v output short-circuit current 7 85 ma v out = gnd or v cc three-state output leakage current 1 a 0.4 v v out 2.4 v
adm2486 rev. c | page 4 of 20 parameter min typ max unit test conditions/comments power supply current logic side 1.3 ma rts = 0 v, v dd1 = 5.5 v 2.9 ma 2 mbps, v dd1 = 5.5 v, see figure 5 10.2 ma 20 mbps, v dd1 = 5.5 v, see figure 5 0.8 ma rts = 0 v, v dd1 = 3 v 1.1 ma 2 mbps, v dd1 = 3 v, see figure 5 4.3 ma 20 mbps, v dd1 = 3 v, see figure 5 bus side 3.0 ma rts = 0 v 53.4 ma 2 mbps, rts = v dd1 , see figure 5 86.7 ma 20 mbps, rts = v dd1 , see figure 5 common-mode transient immunity 1 25 kv/s v cm = 1 kv, transient magnitude = 800 v high frequency, common-mode noise immunity 100 mv v hf = +5 v, ?2 v < v test2 < 7 v, 1 mhz < f test < 50 mhz, see figure 6 1 common-mode transient immunity is the maximum common-mode voltage slew rate that can be sustained while maintaining specificat ion-compliant operation. v cm is the common-mode potential difference between the logic and bus sides. the transient magnitude is the range over which the c ommon-mode is slewed. the common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.
adm2486 rev. c | page 5 of 20 timing specifications 2.7 v v dd1 5.5 v, 4.75 v v dd2 5.25 v, t a = t min to t max , unless otherwise noted. table 2. parameter min typ max unit test conditions/comments driver maximum data rate 20 mbps propagation delay, t plh , t phl 25 45 55 ns r ldiff = 54 ?, c l1 = c l2 = 100 pf, see figure 7 rts-to-de propagation delay 20 35 55 ns see figure 8 pulse width distortion, t pwd 5 ns r ldiff = 54 ?, c l1 = c l2 = 100 pf, see figure 7 and figure 12 switching skew, t skew 2 5 ns r ldiff = 54 ?, c l1 = c l2 = 100 pf, see figure 7 and figure 12 rise/fall time, t r , t f 5 15 ns r ldiff = 54 ?, c l1 = c l2 = 100 pf, see figure 7 and figure 12 enable time 43 53 ns see figure 9 and figure 14 disable time 43 55 ns see figure 9 and figure 14 enable skew, |t azh ? t bzl |, |t azl ? t bzh | 1 3 ns see figure 9 and figure 14 disable skew, |t ahz ? t blz |, |t alz ? t bhz | 2 5 ns see figure 9 and figure 14 receiver propagation delay, t plh , t phl 25 45 55 ns c l = 15 pf, see figure 10 and figure 13 differential skew, t skew 5 ns c l = 15 pf, see figure 10 and figure 13 enable time 3 13 ns r l = 1 k?, c l = 15 pf, see figure 11 and figure 15 disable time 3 13 ns r l = 1 k?, c l = 15 pf, see figure 11 and figure 15 power_valid input enable time 1 2 s disable time 3 5 s
adm2486 rev. c | page 6 of 20 absolute maximum ratings t a = 25c, unless otherwise noted. all voltages are relative to their respective ground. table 3. parameter rating v dd1 ?0.5 v to +7 v v dd2 ?0.5 v to +6 v digital input voltage (rts, re , txd) ?0.5 v to v dd1 + 0.5 v digital output voltage rxd ?0.5 v to v dd1 + 0.5 v de ?0.5 v to v dd2 + 0.5 v driver output/receiver inp ut voltage ?9 v to +14 v operating temperature range ?40c to +85c storage temperature range ?55c to +150c average output current per pin ?35 ma to +35 ma ja thermal impedance 73c/w lead temperature soldering (10 sec) 260c vapor phase (60 sec) 215c infrared (15 sec) 220c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution esd (electrostatic discharge) sensit ive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd prec autions are recommended to avoid performance degrada- tion or loss of functionality.
adm2486 rev. c | page 7 of 20 adm2486 characteristics package characteristics table 4. parameter symbol min typ max unit test conditions resistance (input-output) 1 r i-o 10 12 ? capacitance (input-output) 1 c i-o 3 pf f = 1 mhz input capacitance 2 c i 4 pf input ic junction-to-case thermal resistance jci 33 c/w output ic junction-to-case thermal resistance jco 28 c/w thermocouple located at center of package underside 1 device considered a 2-terminal device: pins 1, 2, 3, 4, 5, 6, 7, and 8 shor ted together, and pins 9, 10, 11, 12, 13, 14, 15, a nd 16 shorted together. 2 input capacitance is from any input data pin to ground regulatory information the adm2486 has been approved by the following organizations: table 5. organization approval type notes ul recognized under 1577 component recognition program. file e214100 in accordance with ul1577, each adm2486 is proof tested by applying an insulation test voltage 3000 v rms for 1 sec (current leakage detection limit = 5 a). csa approved under csa component acceptance notice #5a. file 205078. vde certified according to din en 60747-5-2 (vde 0884 part 2): 2003-01 complies with din en 60747-5-2 (vde 0884 part 2): 2003-01, din en 60950 (vde 0805): 2001-12; en 60950: 2000 file 2471900-4880-0001 in accordance with vde 0884, each adm2486 is proof tested by applying an insulation test voltage 1050 v peak for 1 sec (partial discharge detection limit = 5 pc). insulation and safety-related specifications table 6. parameter symbol value unit conditions rated dielectric insulation volt age 2500 v rms 1-minute duration. minimum external air gap (clearance) l(i01) 7.45 min mm measured from input terminals to output terminals, shortest distance through air. minimum external tracking (creepage) l(i02) 8.1 min mm measured from input terminals to output terminals, shortest distance along body. minimum internal gap (internal clearance) 0.017 min mm insulation distance through insulation. tracking resistance (comparative tracking index) cti >175 v din iec 112/vde 0303 part 1. isolation group iiia material gr oup (din vde 0110, 1/89, table 1).
adm2486 rev. c | page 8 of 20 vde 0884 insulation characteristics this isolator is suitable for basic electrical isolation only within the safety limit data. maintenance of the safety data must be ensured by means of protective circuits. an asterisk (*) on the physical package denotes vde 0884 approval for 560 v peak working voltage. table 7. description symbol characteristic unit installation classification per din vd e 0110 for rated mains voltage 150 v rms i to iv 300 v rms i to iii 400 v rms i to ii climatic classification 40/85/21 pollution degree (din vde 0110, table 1) 2 maximum working insulation voltage v iorm 560 v peak input-to-output test voltage, method b1 v pr 1050 v peak v iorm 1.875 = v pr , 100% production tested, t m = 1 sec, partial discharge < 5 pc input-to-output test voltage, method a (after environmental tests, subgroup 1) v iorm 1.6 = v pr , t m = 60 sec, partial discharge < 5 pc 896 v peak (after input and/or safety test, subgroup 2/3) v iorm 1.2 = v pr , t m = 60 sec, partial discharge < 5 pc v pr 672 v peak highest allowable overvoltage (transient overvoltage, t tr = 10 sec) v tr 4000 v peak safety-limiting values (mximum value allo wed in the event of a failure. see figure 21.) case temperature t s 150 c input current i s , input 265 ma output current i s , output 335 ma insulation resistance at ts, v io = 500 v r s >10 9 ?
adm2486 rev. c | page 9 of 20 pin configuration and function descriptions adm2486 top view (not to scale) v dd1 1 gnd 1 1 2 rxd 3 re 4 v dd2 gnd 2 1 nc b 16 15 14 13 04604-003 5 6 4 12 11 5 7 8 10 9 rts txd pv gnd 1 1 a nc de gnd 2 1 nc = no connect 1 pin 2 and pin 8 are internally connected. either or both may be used for gnd 1 . pin 9 and pin 15 are internally connected. either or both may be used for gnd 2 . figure 2. pin configuration table 8. pin no. mnemonic function 1 v dd1 power supply (logic side). 2, 8 gnd 1 ground (logic side). 3 rd receiver output data. this output is high when (a C b) > 200 mv, and low when (a C b) < C200 mv. the output is three-stated when the re ceiver is disabled, that is, when re is driven high. 4 re receiver enable input. this is an active-low input. driving this input low enables the receiver, and driving it high disables the receiver. 5 rts request to send input. driving this input high enables the driver, an d driving it low disables the driver. 6 txd transmit data input. data to be transmitted by the dri ver is applied to this input. 7 pv power_valid. used during power-up and power-d own. see the applications information section. 9, 15 gnd 2 ground (bus side). 10 de driver enable status output. this output signals the driver enable or disable status to other devices on the bus. de is high when the driver is en abled and low when the driver is disabled. 11, 14 nc no connect. 12 a noninverting driver output/re ceiver input. when the driver is disabled, or when v dd1 or v dd2 is powered down, pin a is put into a high impedance state to avoid overloading the bus. 13 b inverting driver output/receiver input. wh en the driver is disabled, or when v dd1 or v dd2 is powered down, pin b is put into a high impedance state to avoid overloading the bus. 16 v dd2 power supply (bus side).
adm2486 rev. c | page 10 of 20 test circuits 04604-005 v oc r r v od figure 3. driver voltage measurement 04604-006 60 ? v od3 375 ? 375 ? v test figure 4. driver voltage measurement v dd1 de 150 ? gnd 1 a b v dd2 gnd 2 galvanic isolation 04604-004 v dd2 195 ? 110 ? 195 ? gnd 2 rts txd rxd re figure 5. supply-current measurement test circuit v dd1 de gnd 1 a b v dd2 gnd 2 galvanic isolation 04604-010 50 ? 110nf 50 ? v test2 rts txd rxd gnd 2 2.2k ? 100nf 100nf v cm(hf) 470nf 22k ? f test , v hf receive enable 195 ? 110 ? 195 ? v dd2 gnd 2 figure 6. high frequency common-mode noise test circuit 04604-007 c l2 c l1 r ldiff a b figure 7. driver propagation delay v dd1 de gnd 1 a b v dd2 gnd 2 galvanic isolation 04604-008 rts txd rxd re 150 ? 50pf figure 8. rts-to-de propagation delay 04604-009 v cc s2 v out 110 ? 50pf s1 b a txd rts figure 9. driver enable/disable 04604-012 c l v out re a b figure 10. receiver propagation delay 04604-013 v cc s2 v out r l c l +1.5v ?1.5v s1 re re in figure 11. receiver enable/disable
adm2486 rev. c | page 11 of 20 switching characteristics 04604-011 t pahl t pbhl t palh t pblh v dd1 0v vo b a v oh a, b v ol 0.5v dd1 0.5v dd1 t skew t f t r 10% point 10% point 90% point 90% point 1/2vo t skew t pwd = |t palh ? t pahl |, |t pblh ? t pbhl | figure 12. driver propagation delay, rise/fall timing 04604-019 a?b rxd 0v 0v 1.5v 1.5v t plh t skew = |t plh ? t phl | t phl v oh v ol figure 13. receiver propagation delay 04604-021 t lz t zl t hz t zh v oh ? 0.5v v oh + 0.5v a, b a, b rts 0.7v dd1 0.3v dd1 0.5v dd1 0.5v dd1 2.3v 2.3v v ol v oh 0v figure 14. driver enable/disable timing 04604-020 0.7v dd1 0.3v dd1 0.5v dd1 0.5v dd1 v oh v ol o/p low o/p high t lz t zl t hz t zh v oh ? 0.5v v ol + 0.5v 1.5v 1.5v rxd rxd re 0v figure 15. receiver enable/disable timing
adm2486 rev. c | page 12 of 20 typical performance characteristics 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 ?40 25 85 temperature ( c) supply current (ma) 04604-029 i dd1 _rcvr_enable @ 5.5v i dd2 _de_enable @ 5.5v figure 16. unloaded supply current vs. temperature 10 15 20 25 30 35 40 45 50 ?40 25 85 temperature ( c) time (ns) receiver t phl receiver t plh 0 5 04604-026 figure 17. driver propagation delay vs. temperature driver t ahl driver t blh driver t bhl 10 15 20 25 30 35 40 45 50 ?40 25 85 temperature ( c) time (ns) 0 5 driver t alh 04604-027 figure 18. receiver propagation delay vs. temperature 04604-025 ch1 2.00v ch2 2.00v ch3 2.00v ch4 2.00v m20.0ns a ch2 3.12v 1 2 4 t 6.00000ns figure 19. driver/receiver propagation delay, low to high (r ldiff = 54 ?, c l1 = c l2 = 100 pf) 04604-028 ch1 5.00v ch2 2.00v ch3 2.00v ch4 2.00v m20.0ns a ch1 2.60v 1 3 4 t ?444.400ns figure 20. driver/receiver propagation delay, high to low (r ldiff = 54 ?, c l1 = c l2 = 100 pf) case temperature ( c) safety-limiting current (ma) 0 0 350 300 250 200 150 100 50 50 100 150 200 side 1 side 2 04604-018 figure 21. thermal derating curve, dependence of safety-limiting values with case temperature per vde 0884
adm2486 rev. c | page 13 of 20 output current (ma) ?30 ?25 ?20 ?15 ?10 ?5 0 04604-031 output voltage (v) 3.04 3.30 3.56 3.82 4.07 4.31 4.55 4.79 5.00 figure 22. output current vs. receiver output high voltage output current (ma) 5 10 15 20 25 30 35 04604-032 output voltage (v) 0 0.23 0.46 0.69 0.93 1.17 1.42 1.67 1.93 0 2.20 figure 23. output current vs. receiver output low voltage output voltage (v) 4.66 4.68 4.70 4.72 4.74 4.76 4.78 04604-033 temperature ( c) ?40 ?25 ?10 5 20 35 50 65 80 figure 24. receiver output high voltage vs. temperature i = ?4 ma output voltage (v) 0.20 0.22 0.24 0.26 0.28 0.30 0.32 04604-034 temperature ( c) ?40 ?25 ?10 5 20 35 50 65 80 figure 25. receiver output low voltage vs. temperature i = C4 ma
adm2486 rev. c | page 14 of 20 circuit description electrical isolation in the adm2486, electrical isolation is implemented on the logic side of the interface. therefore, the part has two main sections: a digital isolation section and a transceiver section (see figure 26). driver input and request-to-send signals, applied to the txd and rts pins, respectively, and referenced to logic ground (gnd 1 ), are coupled across an isolation barrier to appear at the transceiver section referenced to isolated ground (gnd 2 ). similarly, the receiver output, referenced to isolated ground in the transceiver section, is coupled across the isolation barrier to appear at the rxd pin referenced to logic ground. i coupler technology the digital signals are transmitted across the isolation barrier using i coupler technology. this technique uses chip-scale transformer windings to couple the digital signals magnetically from one side of the barrier to the other. digital inputs are encoded into waveforms that are capable of exciting the primary transformer winding. at the secondary winding, the induced waveforms are then decoded into the binary value that was originally transmitted. 04604-022 isolation barrier v dd2 v dd1 a b de gnd 2 gnd 1 txd rts rxd re encode decode decode decode encode encode d r transceiver digital isolation figure 26. adm2486 digital isolation and transceiver sections truth tables the truth tables in this section use these abbreviations: letter description h high level i indeterminate l low level x irrelevant z high impedance (off) nc disconnected table 9. transmitting supply status inputs output v dd1 v dd2 rts txd a b de on on h h h l h on on h l l h h on on l x z z l on off x x z z l off on x x z z l off off x x z z l table 10. receiving supply status inputs output v dd1 v dd2 a ? b (v) re rxd on on >0.2 l or nc h on on adm2486 rev. c | page 15 of 20 thermal shutdown the adm2486 contains thermal shutdown circuitry that protects the part from excessive power dissipation during fault conditions. shorting the driver outputs to a low impedance source can result in high driver currents. the thermal sensing circuitry detects the increase in die temperature under this condition and disables the driver outputs. this circuitry is designed to disable the driver outputs when a die temperature of 150c is reached. as the device cools, the drivers are re-enabled at a temperature of 140c. receiver fail-safe inputs the receiver input includes a fail-safe feature that guarantees a logic high rxd output when the a and b inputs are floating or open-circuited. magnetic field immunity because i couplers use a coreless technology, no magnetic components are present, and the problem of magnetic saturation of the core material does not exist. therefore, i couplers have essentially infinite dc field immunity. the analysis below defines the conditions under which this may occur. the adm2486s 3 v operating condition is examined because it represents the most susceptible mode of operation. the limitation on the icouplers ac magnetic field immunity is set by the condition in which the induced error voltage in the receiving coil (the bottom coil in this case) is made sufficiently large, either to falsely set or reset the decoder. the voltage induced across the bottom coil is given by ? ? ? ? ? ? ? = 2 n r dt d v ; n n , . . . , 2 , 1 = where, if the pulses at the transformer output are greater than 1.0 v in amplitude: = magnetic flux density (gauss) n = number of turns in receiving coil r n = radius of nth turn in receiving coil (cm) the decoder has a sensing threshold of about 0.5 v; therefore, there is a 0.5 v margin in which induced voltages can be tolerated. given the geometry of the receiving coil and an imposed requirement that the induced voltage is, at most, 50% of the 0.5 v margin at the decoder, a maximum allowable magnetic field is calculated, as shown in figure 27. 04604-016 magnetic field frequency (hz) 1k 10k 100k 100m 1m 10m 100.000 10.000 1.000 0.100 0.010 0.001 maximum allowable magnetic flux density (kgauss) figure 27. maximum allowable external magnetic flux density for example, at a magnetic field frequency of 1 mhz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 v at the receiving coil. this is about 50% of the sensing threshold and does not cause a faulty output transition. similarly, if such an event occurs during a transmitted pulse and is the worst-case polarity, it reduces the received pulse from >1.0 v to 0.75 v. this is well above the 0.5 v sensing threshold of the decoder. figure 28 shows the magnetic flux density values in terms of more familiar quantities such as maximum allowable current flow at given distances away from the adm2486 transformers. 04604-017 magnetic field frequency (hz) 1k 10k 100k 100m 1m 10m distance = 1m distance = 100mm distance = 5mm 1000.00 100.00 0.10 1.00 10.00 0.01 maximum allowable current (ka) figure 28. maximum allowable current for various current-to-adm2486 spacings at combinations of strong magnetic field and high frequency, any loops formed by printed circuit board traces could induce sufficiently large error voltages to trigger the thresholds of succeeding circuitry. care should be taken in the layout of such traces to avoid this possibility.
adm2486 rev. c | page 16 of 20 applications information power_valid input to avoid chatter on the a and b outputs caused by slow power- up and power-down transients on v dd1 (>100 s/v), the device features a power_valid (pv) digital input. this pin should be driven low until v dd1 exceeds 2.0 v. when v dd1 is greater than 2.0 v, this pin should be driven high. conversely, upon power- down, pv should be driven low before v dd1 reaches 2.0 v. if the pv pin is driven with an open-drain output, the recommended value for the pull-up resistor is a 10 k? resistor, bypassed with a 100 pf capacitor to gnd 1 (see figure 30). the power_valid input can be driven, for example, by the output of a system reset circuit such as the adm809z, which has a threshold voltage of 2.32 v. adm809z adm2486 v dd1 pv gnd 1 v dd1 reset reset v dd1 t por 2.32v 2.0v 2.32v 2.0v 04604-023 figure 29. driving pv with adm809z adm809z adm2486 v dd1 pv gnd 1 v dd1 reset reset v dd1 t por 2.32v 2.0v 2.32v 2.0v 04604-030 100pf 10k ? figure 30. driving pv with an open-drain output
adm2486 rev. c | page 17 of 20 isolated power supply circuit the adm2486 requires isolated power capable of 5 v at 100 ma to be supplied between the v dd2 and gnd 2 pins. if no suitable integrated power supply is available, a discrete circuit, such as the one in figure 31, can be used. a center-tapped transformer provides electrical isolation. the primary winding is excited with a pair of square waveforms that are 180 out of phase with each other. a pair of schottky diodes and a smoothing capacitor are used to create a rectified signal from the secondary winding. the adp667 linear voltage regulator provides a regulated power supply to the adm2486s bus-side circuitry. to create the pair of square waves, a d-type flip-flop with complementary q/ q outputs is used. the flip-flop can be connected so that output q follows the clock input signal. if no local clock signal is available, a simple digital oscillator can be implemented with a hex-inverting schmitt trigger and a resistor and capacitor. in this case, values of 3.9 k? and 1 nf generate a 364 khz square wave. a pair of discrete nmos transistors, switched by the q/ q flip-flop outputs, conduct current through the center tap of the primary transformer, winding in an alternating fashion. 04604-024 isolation barrier v cc 78253 sd103c sd103c 22 f bs107a bs107a 10 f 5v out in set gnd shdn v cc v dd1 v dd2 gnd 1 gnd 2 clk q q d pr clr 74hc74a 100nf v cc v cc 100nf 74hc14a 3.9k ? 1nf adp667 adm2486 figure 31. isolated power supply circuit
adm2486 rev. c | page 18 of 20 outline dimensions controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design compliant to jedec standards ms-013aa seating plane 0.30 (0.0118) 0.10 (0.0039) 0.51 (0.0201) 0.31 (0.0122) 2.65 (0.1043) 2.35 (0.0925) 1.27 (0.0500) bsc 16 9 8 1 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 10.50 (0.4134) 10.10 (0.3976) 8 0 0.75 (0.0295) 0.25 (0.0098) 45 1.27 (0.0500) 0.40 (0.0157) 0.33 (0.0130) 0.20 (0.0079) coplanarity 0.10 figure 32. 16-lead standard small outline package [soic] wide body (rw-16) dimensions shown in millimeters and (inches) ordering guide model data rate (mbps) temperature range pa ckage description quantity package option adm2486brw 20 ?40c to +85c 16-lead, wide body soic 47 rw-16 adm2486brw-reel 20 ?40c to +85c 16-le ad, wide body soic 1,000 rw-16 adm2486brwz 1 20 ?40c to +85c 16-lead, wide body soic 47 rw-16 ADM2486BRWZ-REEL 1 20 ?40c to +85c 16-lead, wide body soic 1,000 rw-16 1 z = pb-free part.
adm2486 rev. c | page 19 of 20 notes
adm2486 rev. c | page 20 of 20 notes ? 2005 analog devices, inc. all ri ghts reserved. trademarks and registered trademarks are the prop erty of their respective owners. d04604C0C3/05(c)

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